Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores and multiple logical processors present on individual integrated circuits. A processor or integrated circuit typically comprises a single processor die, where the processor die may include any number of processing resources, such as cores, threads, and/or logical processors.
Each of the processing resources is typically associated with a virtual or linear address space, which translates into a portion of physical system memory. As an example, a page table structure is utilized to translate virtual addresses into physical addresses. Usually, in a page table structure, a page table base register (PTBR) stores a base address for a processing resource. As a result, each processing resource potentially includes a different linear address view of physical memory. However, in many circumstances, a portion or all of a processing resource's virtual address space overlaps with other processing resources. For example, different types of sharing include shared objects that have the same virtual address in multiple address spaces and shared object that have different virtual address spaces in multiple address spaces.
Because traversing a memory data structure, such as a page table, is expensive, hardware mechanisms, such as a translation buffer, are used to store recent translations. Previously, when a translation buffer is shared between processing resources, a portion of the translation buffer is dedicated to each resource or the entire translation buffer is open to each resource, but only associates a single entry with a single processing resource. As a result, expensive translations are potentially conducted for one resource, when the same translation exists in the translation buffer for another resource.
As an example, a first processing resource accesses a translation buffer to obtain a translation for a first virtual address. If a translation for the first virtual address associated with the first processing resource is not present, a miss to the translation buffer occurs and the expensive translation is done. Yet, if a second virtual memory space for a second processing resource overlaps a first virtual address space for the first processing resource, the correct translation of the virtual address may be present in the translation buffer, but associated with the second resource. However, since current translation buffers do not share access to entries, the expensive page table translation is conducted instead of allowing hardware to share an existing translation entry.